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上課地點：【上海】：同濟大學(滬西)/新城金郡商務樓(11號線白銀路站) 【深圳分部】：電影大廈(地鐵一號線大劇院站)/深圳大學成教院【北京分部】：北京中山學院/福鑫大樓【南京分部】：金港大廈(和燕路) 【武漢分部】：佳源大廈（高新二路）【成都分部】：領館區1號（中和大道）【沈陽分部】：沈陽理工大學/六宅臻品【鄭州分部】：鄭州大學/錦華大廈【石家莊分部】：河北科技大學/瑞景大廈【廣州分部】：廣糧大廈【西安分部】：協同大廈
最近開課時間(周末班/連續班/晚班）：Virtuoso Chip Assembly Router培訓：2020年3月16日

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　　Virtuoso Chip Assembly Router培訓

培訓方式以講課和實驗穿插進行

課程描述：

Virtuoso Chip Assembly Router Course Description

This course explores the basic design flow for device-level and chip-level routing with?Virtuoso Chip Assembly Router. You will focus on methods of solving typical problems?while routing a top-level block design.

The highlights of this class include the following:

Learn about available translators for the Virtuoso Chip Assembly Router
Find, analyze, and solve typical problems
Explore component placement techniques
Understand routing techniques (automatic and interactive)
Create rules for clearance, timing, and noise
Explore power routing capabilities
Route device-level designs
Route a chip-level design

Audience

DSM Designers
Chip Designers
The primary audience includes experienced chip assembly users who are interested in improving block and chop assembly routing techniques for their design flows

Prerequisites

Students should already have knowledge of:

Virtuoso Layout Editor
Virtuoso XL Layout Editor

Students should have practical experience with:

UNIX OS

Course Agenda

Introduction
Preparing and translating data
Virtuoso Chip Assembly Router environment
Interactive placement
Interactive routing
Using rules and levels
How the autorouter works
Creating device-level designs
Creating chip-assembly deisgner