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1. 嵌入式語言之使用 SystemVerilog 進行驗證培訓
   ? 使用 SystemVerilog 進行驗證培訓 Verification with System Verilog
   Who Should Attend?
   Hardware and verification engineers
2. Course Outline
   1
   Introduction to SystemVerilog for Verification
   Data Types
   Tasks and Functions
   Lab 1:?Implementing Tasks and Functions
   SystemVerilog Verification Building Blocks
   Lab 2:?Connecting the Testbench to the DUT
   Object-Oriented Modeling
   Lab 3:?Object-Oriented Modeling
   2
   Randomization
   Lab 4:?Randomization
   Coverage
   Lab 5:?Coverage
   Assertions
   Lab 6:?Assertions
   Direct Programming Interface
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